Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.
A DRAM cell without a capacitor has been investigated previously. Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Chatterjee et al. have proposed a Taper Isolated DRAM cell concept in “Taper Isolated Dynamic Gain RAM Cell”, P. K. Chatterjee et al., pp. 698-699, International Electron Devices Meeting, 1978 (“Chatterjee-1”), “Circuit Optimization of the Taper Isolated Dynamic Gain RAM Cell for VLSI Memories”, P. K. Chatterjee et al., pp. 22-23, IEEE International Solid-State Circuits Conference, February 1979 (“Chatterjee-2”), and “DRAM Design Using the Taper-Isolated Dynamic RAM Cell”, J. E. Leiss et al., pp. 337-344, IEEE Journal of Solid-State Circuits, vol. SC-17, no. 2, April 1982 (“Leiss”), which are hereby incorporated herein, in their entireties, by reference thereto. The holes are stored in a local potential minimum, which looks like a bowling alley, where a potential barrier for stored holes is provided. The channel region of the Taper Isolated DRAM cell contains a deep n-type implant and a shallow p-type implant. As shown in “A Survey of High-Density Dynamic RAM Cell Concepts”, P. K. Chatterjee et al., pp. 827-839, IEEE Transactions on Electron Devices, vol. ED-26, no. 6, June 1979 (“Chatterjee-3”), which is hereby incorporated herein, in its entireties, by reference thereto, the deep n-type implant isolates the shallow p-type implant and connects the n-type source and drain regions.
Terada et al. have proposed a Capacitance Coupling (CC) cell in “A New VLSI Memory Cell Using Capacitance Coupling (CC) Cell”, K. Terada et al., pp. 1319-1324, IEEE Transactions on Electron Devices, vol. ED-31, no. 9, September 1984 (“Terada”), while Erb has proposed Stratified Charge Memory in “Stratified Charge Memory”, D. M. Erb, pp. 24-25, IEEE International Solid-State Circuits Conference, February 1978 (“Erb”), both of which are hereby incorporated herein, in their entireties, by reference thereto.
DRAM based on the electrically floating body effect has been proposed both in silicon-on-insulator (SOI) substrate (see for example “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”), “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 (“Okhonin”) and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002 (“Ohsawa”), which are hereby incorporated herein, in their entireties, by reference thereto) and in bulk silicon (see for example “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM”, R. Ranica et al., pp. 128-129, Digest of Technical Papers, 2004 Symposium on VLSI Technology, June 2004 (“Ranica-1”), “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-Cost eDRAM Applications”, R. Ranica et al., 2005 Symposium on VLSI Technology, Digest of Technical Papers (“Ranica-2”), “Further Insight Into the Physics and Modeling of Floating-Body Capacitorless DRAMs”, A. Villaret et al, pp. 2447-2454, IEEE Transactions on Electron Devices, vol. 52, no. 11, November 2005 (“Villaret”), “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate”, R. Pulicani et al., pp. 966-969, 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (“Pulicani”), which are hereby incorporated herein, in their entireties, by reference thereto).
Widjaja and Or-Bach describes a bi-stable SRAM cell incorporating a floating body transistor, where more than one stable state exists for each memory cell (for example as described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto). This bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination. During operation as a bi-stable SRAM, the floating body transistor memory cell stores charge in the floating body in order to achieve two stable states. In a low stable state or state 0 the floating body is at a low state or discharged to some voltage such as 0 v. In a high stable state or state 1 the floating body is charged to a higher stable state such as 0.5 V. The low stable state will consume little to no standby power beyond a typical NMOS transistor sub threshold leakage. The high stable state however will consume a standby current since a vertical bipolar is enabled to counter any leakage to the floating body.